I. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device wherein a thick field insulating film is formed in a field region so as to have a flat surface, and the thickness of an insulating film at the peripheral portion of the element formation region is controlled.
II. Description of the Prior Art
In a conventional semiconductor device using silicon, particularly a MOS device, a thick insulating film is formed in a field region between element formation regions so as to prevent incomplete insulation due to a parasitic channel and to decrease parasitic capacitance in a junction.
Selective oxidation is generally used for element isolation. According to this technique, an antioxidant mask (typically, a silicon nitride film) is formed to cover a prospective element formation region. Thermal oxidation is then performed at a high temperature to leave a thick oxide film only in the field region. However, in selective oxidation, a field oxide film undercuts the silicon nitride film, thus forming a so-called "bird's beak" during oxidation at a high temperature. This results in a dimensional error of the element formation region and hence precludes a high packing density of the integrated circuit. Furthermore, a stepped portion which has a height of about 0.3 to 0.5 .mu.m is formed at a boundary between the field region and the element formation region. This stepped portion results in the degradation of lithographic precision and poor step coverage of the wiring layer.
On the other hand, a liftoff technique is known which eliminates both the bird's beak and the stepped portion while forming a thick oxide film for element isolation. According to the liftoff technique, the field region is etched, thus forming a groove and a field oxide film is formed therein. A conventional liftoff technique will be briefly described with reference to FIGS. 1(A) to 1(G). As shown in FIG. 1(A), a thermal oxide film 12 is formed on a silicon substrate 11, and an Al film 13 is formed thereon. Thereafter, a photoresist film 14 is formed on the Al film 13 by photoetching. The thermal oxide film 12 and the Al film 13 are etched using the photoresist film 14 as a mask. After the photoresist film 14 is removed, the silicon substrate 11 is selectively etched by reactive ion etching (RIE) using the Al film 13 as a mask, thus forming a groove of a depth corresponding to the thickness of a prospective field insulating film, as shown in FIG. 1(B). Using the Al film 13 as a mask, a p-type impurity such as boron is ion-implanted in the exposed portion of the silicon substrate 11, thereby forming a p.sup.+ -type inversion preventive layer (field stopper) 15. It should be noted that the impurity has the same conductivity type as that of the silicon substrate but has a higher concentration. Thereafter, as shown in FIG. 1(C), a thick plasma CVD-SiO.sub.2 film 16.sub.1 is formed to cover the entire surface to a thickness greater than the depth of the groove. The CVD-SiO.sub.2 film 16.sub.1 is then etched by an aqueous solution of ammonium fluoride for one minute. A film portion of the CVD-SiO.sub.2 film 16.sub.1 which is formed on the side wall of the element formation region is etched faster than the remaining portion of the CVD-SiO.sub.2 film 16.sub.1 . Therefore, the SiO.sub.2 film on the side wall is selectively etched, so that a narrow groove is formed. Subsequently, the Al film 13 is removed to lift off the CVD-SiO.sub.2 film portion thereon, thus obtaining a structure as shown in FIG. 1(D). As shown in FIG. 1(E), a CVD-SiO.sub.2 film 16.sub.2 is formed to cover the entire surface including the narrow groove. A photoresist film 17 is then applied to the entire surface so as to obtain a flat surface. It should be noted that the photoresist film is flowable and has the same etching rate as that of the CVD-SiO.sub.2 films 16.sub.1 and 16.sub.2 . As shown in FIG. 1(F), the photoresist film 17 and the CVD-SiO.sub.2 films 16.sub.1 and 16.sub.2 are then uniformly etched to expose the element formation region. FIG. 1(G) shows a structure wherein a gate electrode 19 is formed through a gate oxide film 18 in the element formation region.
According to this conventional method, the size of the element formation region is defined by the size of a photoetched mask which is used for etching the silicon substrate 11 by reactive ion etching. Therefore, a dimensional error of the element formation region can be substantially eliminated. Furthermore, the field oxide film has a flat surface, thereby greatly improving lithographic precision and allowing good step coverage of the wiring layer.
However, when the conventional liftoff technique is used to manufacture an MOS transistor which has a gate width of 1 .mu.m or less, a potential at an end of the substrate portion along a width W of the gate electrode 19 is increased with respect to a central substrate portion therealong, so that the obtained MOS transistor tends to have a low threshold voltage. The threshold voltage thus depends on the gate width, thereby precluding a high packing density. Furthermore, since the carriers are concentrated at the periphery of the element formation region, the MOS transistor is unstably operated, thus degrading element reliability.